Press Releases
SMIC Adopts Cadence DFM Solutions for 65- and 45-Nanometer IP/Library Development and Full Chip Production
Shanghai [2009-10-19]
Cadence Model-Based Litho Physical and Litho Electrical Analyzer Solutions Provide Fast and Accurate Silicon-Validated Full-Chip Electrical DFM Verification Flow
SAN JOSE, Calif., Oct. 19, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI and SEHK: 0981.HK) has adopted Cadence? Litho Physical Analyzer and Cadence Litho Electrical Analyzer to more accurately predict the impact of stress and lithographic variability on the performance of 65- and 45-nanometer semiconductor designs. The Cadence Litho Electrical Analyzer -- the semiconductor industry’s first electrical DFM solution in production at leading semiconductor companies from 90 nanometers to 40 nanometers – combined with Cadence Litho Physical Analyzer to create a flow that accurately predicted final silicon results.
Previously, the electrical behavior of individual cells and libraries could be pre-characterized in a single context that could be consistently applied to a given design based on the targeted process technology. At 65 nanometers and below, each placement of a cell creates its own set of physical and electrical variabilities relative to its neighboring cells or surroundings. This “context dependent variability” is emerging as a critical issue which can cause the chip to fail. Cadence Encounter? Digital Implementation System (EDI) System seamlessly integrates both the Litho Physical Analyzer and Litho Electrical Analyzer for rigorous context-dependent physical and electrical signoff of cells prior to full chip implementation. The flow leverages model-based physical and electrical design for manufacturing (DFM) technologies to improve the quality and reliability of standard cell libraries, intellectual property (IP) cores, and full chip to increase manufacturing yield in full chips.
“The necessity to address physical and electrical variation at 65 and 45 nanometers requires a holistic approach that starts at the cell level and considers the entire context of the design,” said Max Liu, VP of SMIC Design Services Center. “With the Cadence DFM flow, we could analyze cell and IP variability and accurately model their performance in real silicon. By characterizing and reducing the variability, our customers will be able to reduce guard-banding and to produce higher quality silicon. The solution also enables near-linear scalability, which is necessary for a full-chip electrical DFM verification flow.”
Cadence has developed one of the industry’s most complete design side DFM prevention, analysis, and signoff methodologies, including design-side optimizations with Encounter Digital Implementation System. It is also being used for variability modeling of 32- and 28-nanometer libraries. “Fast, accurate context-dependent variability modeling of cells for both lithography and stress effects is key to implementing production-worthy designs at 65 nanometers and below,” said Dr. Chi-Ping Hsu, senior vice president of research and development for the Implementation Group at Cadence. “Numerous first silicon successes have already proven the value of DFM analysis tools for high-volume semiconductor designs.”
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
About SMIC
Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in Mainland China, providing integrated circuit (IC) foundry and technology services at 0.35um to 45nm. Headquartered in Shanghai, China, SMIC has a 300mm wafer fabrication facility (fab) and three 200mm wafer fabs in its Shanghai mega-fab, two 300mm wafer fabs in its Beijing mega-fab, a 200mm wafer fab in Tianjin, a 200mm fab under construction in Shenzhen, and an in-house assembly and testing facility in Chengdu. SMIC also has customer service and marketing offices in the U.S., Europe, and Japan, and a representative office in Hong Kong. In addition, SMIC manages and operates a 200mm wafer fab in Chengdu owned by Cension Semiconductor Manufacturing Corporation and a 300mm wafer fab in Wuhan owned by Wuhan Xinxin Semiconductor Manufacturing Corporation. For more information, please visit http://www.3dsentson.com.
Cadence, the Cadence logo, and Encounter are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Dan Holden
Cadence Design Systems, Inc.
(408) 944-7457
holden@cadence.com
International Media
Beverly Liu
SMIC Investor Relations
Tel: +86 (21) 3861 0000
E-mail: Beverly_Liu@3dsentson.com
China Media
Angela Miao
SMIC Public Relations
Tel: +86 (21) 3861 0000
E-mail: Angela_Miao@3dsentson.com
Cadence Model-Based Litho Physical and Litho Electrical Analyzer Solutions Provide Fast and Accurate Silicon-Validated Full-Chip Electrical DFM Verification Flow
SAN JOSE, Calif., Oct. 19, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI and SEHK: 0981.HK) has adopted Cadence? Litho Physical Analyzer and Cadence Litho Electrical Analyzer to more accurately predict the impact of stress and lithographic variability on the performance of 65- and 45-nanometer semiconductor designs. The Cadence Litho Electrical Analyzer -- the semiconductor industry’s first electrical DFM solution in production at leading semiconductor companies from 90 nanometers to 40 nanometers – combined with Cadence Litho Physical Analyzer to create a flow that accurately predicted final silicon results.
Previously, the electrical behavior of individual cells and libraries could be pre-characterized in a single context that could be consistently applied to a given design based on the targeted process technology. At 65 nanometers and below, each placement of a cell creates its own set of physical and electrical variabilities relative to its neighboring cells or surroundings. This “context dependent variability” is emerging as a critical issue which can cause the chip to fail. Cadence Encounter? Digital Implementation System (EDI) System seamlessly integrates both the Litho Physical Analyzer and Litho Electrical Analyzer for rigorous context-dependent physical and electrical signoff of cells prior to full chip implementation. The flow leverages model-based physical and electrical design for manufacturing (DFM) technologies to improve the quality and reliability of standard cell libraries, intellectual property (IP) cores, and full chip to increase manufacturing yield in full chips.
“The necessity to address physical and electrical variation at 65 and 45 nanometers requires a holistic approach that starts at the cell level and considers the entire context of the design,” said Max Liu, VP of SMIC Design Services Center. “With the Cadence DFM flow, we could analyze cell and IP variability and accurately model their performance in real silicon. By characterizing and reducing the variability, our customers will be able to reduce guard-banding and to produce higher quality silicon. The solution also enables near-linear scalability, which is necessary for a full-chip electrical DFM verification flow.”
Cadence has developed one of the industry’s most complete design side DFM prevention, analysis, and signoff methodologies, including design-side optimizations with Encounter Digital Implementation System. It is also being used for variability modeling of 32- and 28-nanometer libraries. “Fast, accurate context-dependent variability modeling of cells for both lithography and stress effects is key to implementing production-worthy designs at 65 nanometers and below,” said Dr. Chi-Ping Hsu, senior vice president of research and development for the Implementation Group at Cadence. “Numerous first silicon successes have already proven the value of DFM analysis tools for high-volume semiconductor designs.”
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
About SMIC
Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in Mainland China, providing integrated circuit (IC) foundry and technology services at 0.35um to 45nm. Headquartered in Shanghai, China, SMIC has a 300mm wafer fabrication facility (fab) and three 200mm wafer fabs in its Shanghai mega-fab, two 300mm wafer fabs in its Beijing mega-fab, a 200mm wafer fab in Tianjin, a 200mm fab under construction in Shenzhen, and an in-house assembly and testing facility in Chengdu. SMIC also has customer service and marketing offices in the U.S., Europe, and Japan, and a representative office in Hong Kong. In addition, SMIC manages and operates a 200mm wafer fab in Chengdu owned by Cension Semiconductor Manufacturing Corporation and a 300mm wafer fab in Wuhan owned by Wuhan Xinxin Semiconductor Manufacturing Corporation. For more information, please visit http://www.3dsentson.com.
Cadence, the Cadence logo, and Encounter are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Dan Holden
Cadence Design Systems, Inc.
(408) 944-7457
holden@cadence.com
International Media
Beverly Liu
SMIC Investor Relations
Tel: +86 (21) 3861 0000
E-mail: Beverly_Liu@3dsentson.com
China Media
Angela Miao
SMIC Public Relations
Tel: +86 (21) 3861 0000
E-mail: Angela_Miao@3dsentson.com
